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LOGIC DESIGN LAB FINAL PROJECT

Marlovis Abreu Panther ID 6210161

mabre064@fiu.edu

LOGIC DESIGN LAB FINAL PROJECT

The following project implements a 4-bit binary multiplier by using a 4-bit ripple adder.

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Logic Diagram and Equations for a 4-bit Binary Multiplier Using a 4-bit Ripple Adder

Logic Diagram

VHDL Code for the 4-bit Binary Multiplier

Test Bench

Implementation and Simulation Results

Schematic Obtained from Xilinx Vivado Simulation Results

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CONTACT

mabre064@fiu.edu

Panther ID 6210161

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